1. Field of the Invention
The present invention relates to scan chains in field programmable gate arrays, and more specifically to making scan chains available to the end user.
2. Background of the Invention
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing all Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain one or two registers or flip flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
FPGAs typically include a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Once a specific configuration of an FPGA has been decided upon, it can be configured to perform that one specific function.
The user programmable switches in an FPGA can be implemented in various technologies, such as ONO antifuse, M—M antifuse, SRAM memory cell, Flash EPROM memory cell, and EEPROM memory cell. FPGAs that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of an FPGA can be reprogrammed repeatedly. In this scenario, an NMOS transistor is typically used as the switch to either connect or disconnect two selected points (A, B) in the circuit. The NMOS' source and drain nodes are connected to points A, B respectively, and its gate node is directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical “1” or “0”, the switch can be turned on or off and thus point A and B are either connected or disconnected. Thus, the ability to program these switches provides for a very flexible device.
FPGAs can store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory CM determines the cells' functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.
In general, an FPGA is one type of programmable logic device (PLD), i.e., a device that contains many gates or other general-purpose cells whose interconnections can be configured or “programmed” to implement any desired combinational or sequential function. As its name implies, an FPGA is “field-programmable”, meaning that the device is generally programmed by designers or end users “in the field” via small, low-cost programming units. This is in contrast to mask programmable devices which require special steps in the IC chip-manufacturing process.
A field-programming unit typically uses design software to program the FPGA. The design software compiles a specific user design, i.e., a specific configuration of the programmable switches desired by the end-user, into FPGA configuration data. The design software assembles the configuration data into a bit stream, i.e., a stream of ones and zeros, that is fed into the FPGA and used to program the configuration memories for the programmable switches. The bit stream creates the pattern of the data in the configuration memory CM that determines whether each memory cell stores a “1” or a “0”. The stored bit in each CM controls whether its associated transistor switch is turned on or off. End users typically use design software to test different designs and run simulations for FPGAs.
Designers of FPGAs (as well as other PLDs) often provide their circuit designs to IC manufacturers who typically manufacture the FPGAs in two different ways. First, an FPGA design may be manufactured as its own chip with no other devices being included in the IC package. Second, an FPGA design may be embedded into a larger IC. An example of such a larger IC is a system on a chip (SOC) that includes the embedded FPGA as well as several other components. The several other components may include, for example, a microprocessor, memory, arithmetic logic unit (ALU), state machine, etc. In this scenario the embedded FPGA may be only a small part of the whole SOC.
Whether a FPGA is to be manufactured as its own IC or embedded into a larger IC (e.g. a SOC), the intended application/use of the IC will determine the size and complexity of the FPGA that is needed. Because conventional FPGAs are typically designed for their intended application/use, an FPGA designed to fulfill a need for a small FPGA must be substantially redesigned for use where a larger FPGA is needed.
A FPGA array logic structure may also contain scan chains which are implemented by the FPGA manufacturer for manufacturing tests. These tests are performed to test the circuitry in the FPGA logic structure. More specifically, the scan chains implement a full scan of all the registers in the FPGA array. In the past, if the FPGA user had a requirement to implement a scan on his application circuit, he would insert an additional scan chain that uses the FPGA logic resources to create the scan chain. This would require an additional three input function. For example, a simple multiplexer would be implemented in front of every register. This leads to a significant area and performance impact.
Hence, there is a need for a device and method which will provide access for the user to the scan chain previously available only to the manufacturer. Therefore, it would be highly advantageous to the user to have a means of access to the scan chains previously available only to the manufacturer. This would enable the user to implement a scan on his application circuit and thus, a full scan of all the registers in the FPGA logic structure.